The above said technique uses internal RAM blocks of the FPGA to store the samples ... SoC Designs with FPGA Prototyping”, IEEE HPCA-11: Workshop on Architecture Research using FPGA Platforms, Feb.

The IP core processor must be implemented within FPGA device characterized by a heterogeneous architecture (logic elements, DSP blocks, RAM blocks, I/O pin…) and by a size able to integrate the HW and ...